Race Around Condition in JK Flip-Flop

In the level triggered JK flip-flop when, when both J and K input are 1 and when the ON time of the clock is more than the propagation delay of the flip-flop then the output of the flip-flop will toggle continuously between ‘1’ and ‘0’. And because of that, it is difficult to predict the output of the flip-flop once the clock becomes low. The race around condition in undesirable condition in the flip-flop, and should be avoided to get the reliable flip-flop output.

Race Around Condition in JK Flip-Flop

Using the JK flip-flop in master slave configuration, this race around condition can be avoided.

Circuit Diagram of Master Slave JK Flip-Flop

Circuit Diagram of Master Slave JK Flip-Flop

As shown in the above figure, it consist of two gated SR latches. The first latch act as a master latch and the second latch act as a slave latch. The output of the master latch is connected to the slave latch. The Q’ output of the slave latch is connected back to the master latch where J input is applied and similarly, Q output is connected back where the K input is applied. The clock signal to the slave latch is applied through an inverter. That means when clock signal is high then master is enabled and slave is disabled. And similarly, when clock is low then slave is active and master is disabled.

Working of Master Slave JK Flip-Flop

Let’s understand the working of Master Slave JK flip-flop using timing diagram.

Timing Diagram of Master Slave JK Flip-Flop

Here, initially it has been assumed that the outputs of both master and slave are 0. (Both M and Q are 0). When the clock signal is high then master latch will get enabled and will respond to the input signals. In this case, initially during the first clock, J = 0 and K = 1. So, output of the master latch will be 0. During ON time of the clock, the slave latch will remain disabled and it will hold its current state. Similarly, during the OFF time of the clock, the master will get disabled and it will hold its current state. And at the same time, the slave latch will become active and will follow the master output. That means, the slave latch is following the master output during the off time of the clock. Or in other words, the slave latch follows the master output after the delay of T_ON . Where T_ON is the ON time of the clock signal. This cycle repeats at every clock cycle.

During the ON time of the second clock, since J = 1 and K = 0, so master output M = 1. And the slave output Q will remain 0. (Since it is disabled) The slave latch will follow the master output during the OFF time of the clock. From the timing diagram, you can see that, the slave is following the master output after the delay of T_ON.

For more information, please go through this video on the master slave flip-flop.

Master Slave SR Flip-Flop and D Flip-Flop

Similar to the master slave JK flip-flop, the master slave D flip-flop and SR flip-flop can be designed.

The circuit diagram of the master slave SR flip-flop is shown below.

Master Slave SR Flip-Flop

In a simplified manner, this is how it can be represented.

Similarly, using two gated D latches, the master slave D flip-flop can be designed.

Master Slave D Flip-Flop

The master slave flip-flop circuit works correctly when the input is constant during the ON time of the clock. If the input signal changes during the ON time of the clock, then slave will not be able to follow the master output. The same is shown in the below timing diagram.

As you can see in the timing diagram, during the second clock cycle, the D input is changing during the ON time of the clock. Since the master is ON at that time, so master will follow the change in the input signal. But the slave will not be follow that input change. Because the slave is following the master output during the OFF time of the clock. Just at the end of the ON period of the second clock, the master output M is 1, so slave will follow the same output. That means, the slave is not able to follow the master output completely when the input is changing during the ON time of the clock.

That means, to use the master slave flip-flop in a correct manner, we need to ensure that the input is not changing during the ON time of the clock.

The post Master Slave Flip-Flop Explained appeared first on ALL ABOUT ELECTRONICS.

In the SR Flip-Flop, when both inputs S and R are 1 then the output of the flip-flop is indeterminate. That issue can be resolved using the JK Flip-Flop. Similar to the SR Flip-Flop, the JK flip-flop has two inputs. And using the two inputs the flip-flop can be set, reset, hold (memory) or toggled. Unlike the SR flip-flop, in the JK flip-flop, when both inputs J and K are 1 then the output of the flip-flop toggles. The symbol of edge triggered JK flip-flop and its truth table is shown below.

JK Flip-Flop Symbol and Truth Table

In the JK flip-flop, at the rising edge of the clock, when J = 0 and K = 0 then flip-flop retains (holds) the current state. When J = 0 and K = 1, then flop-flop resets to 0. When J = 1 and K = 0, then flip-flop sets the output to 1. And when J = 1 and K = 1 then output of the flip-flop toggles. When the clock signal is low, then irrespective of the value of J and K inputs, the flop-flop retains the present state. The detailed truth table with all different possibilities of Qn, J and K inputs are shown below, where Qn is the present state and Q_n+1 is the next state of the flip-flop.

JK Flip-Flop Truth Table

The negative edge triggered JK flip-flop is similar to the positive edge triggered flip-flop. But it responds to the inputs only at the falling edge of the clock. The symbol and truth table of negative edge triggered flip-flop is shown below.

Symbol and Truth Table of Negative Edge Triggered JK Flip-Flop

JK Flip-Flop Circuit Diagram

With the little modification in the circuit of the SR flip-flop circuit, it can be used as the JK flip-flop. The circuit of JK flip-flop is shown below.

Circuit Diagram of Positive Edge Triggered JK Flip-Flop

As you can see from the circuit diagram, in the RS flip-flop circuit, the K input is applied in place of the R input while the J input is applied in place of the S input. Moreover, there is a feedback from output to input side. The Q output is connected back the AND gate where the K input is applied while the Q’ output is connected back to the AND gate where the J input is applied. Here the clock transition circuit generates the narrow pulses at the every clock transition. The same is applied to the enable input of the latch. And in this way, the gated latch behaves as an edge triggered flip-flop.

The same circuit can also be implemented using the NAND gates. The circuit diagram of the JK flip-flop with the NAND gates is shown below.

Circuit Diagram of Positive Edge Triggered JK Flip-Flop (using NAND gates)

JK Flip-Flop Characteristic Equation

The characteristic equation shows the output of the flip-flop Q _n+1 in terms of the present state Q _n and the current inputs J and K. The characteristic table of the JK flip-flop is shown below.

The characteristic Table of JK Flip-Flop

As per the characteristic equation, the output Q _n+1 is ‘1’ for 4 different input combinations. ( 4 minterms). Using the K-map, the algebraic expression can be simplified further.

As per the K-map, after the simplification the output of the flip-flop or the characteristic equation

JK Flip-Flop Excitation Table

The excitation table of the flip-flop shows the required excitation to the flip-flop, or the required input to the flip-flop, to go from the given state to the next particular state. The excitation table of the JK flip-flop is shown below. In the table, ‘X’ represents that the value of input variable can be either ‘0’ or ‘1’.

Excitation Table of JK Flip-Flop

For more information, please check the video on JK Flip-Flop

JK Flip-Flop Timing Diagram

The below timing diagram shows, how the positive edge triggered JK Flip-Flop behaves when J and K input changes with time. Since it is a positive edge triggered flip-flop, so it will respond to the inputs only at the rising edge of the clock.

Timing Diagram of JK Flip-Flop

At the first rising edge of the clock, when J = 0 and K = 1, then output Q becomes 0 and it remains in that state until next rising edge. In between, even if the input changes, the flip-flop does not responds to the input changes.

At the second rising edge, since J = 1 and K = 0, the output of the flip-flop becomes 1. And it remains in that state until next rising edge.

At the third rising edge, since both J and K inputs are 1, the output of the flip-flop toggles and it becomes 0.

Race Around Condition in JK Flip-Flop

In the level triggered JK Flip-Flop, when J=K=1, and the ON time of the clock is more than the propagation delay of the JK Flip-Flop ,then because of the feedback from output to the input, the output of the flip-flop may toggle continuously between ‘1’ and ‘0’. This condition is known as the Race Around condition. Because of the Race Around Condition’, we cannot predict the output of the flip-flop at the end of the clock. It can be either ‘0’ or ‘1’. That’s why this Race Around Condition is undesired in the JK Flip-Flop. The issue of Race Around Condition can be resolved using the Master-Slave Flip-Flop. The below diagram shows the Race Around Condition in the JK Flip-Flop.

Race Around Condition in the JK Flip-Flop

The post JK Flip-Flop Explained | Race Around Condition in JK Flip-Flop | JK Flip-Flop Truth Table, Excitation table and Timing Diagram appeared first on ALL ABOUT ELECTRONICS.