What is CMOS Logic ?

If you see any logic gate then its characteristics like its voltage levels, fan-out, speed, power consumption depends on the technology which is used to design these logic gates.
There are different logic families like RTL, DTL, TTL and MOS, ECL logic family. Some of them are already obsolete, and are not used in the design these days. While some of the logic families like TTL, ECL, MOS and CMOS logic families are quite popular and widely used in the digital circuits.

CMOS stands for Complementary Metal Oxide Semiconductor. And CMOS based logic gates uses complementary pair of NMOS and PMOS transistors. When MOS transistors are used as logic gate then they are used as a switch.

In both NMOS and PMOS transistor, the voltage applied between the gate and source acts as a control voltage.

By controlling the gate to source voltage, PMOS and NMOS transistor can be used as a switch. And they can be used to design a logic gate.

CMOS logic uses both NMOS and PMOS transistors. The PMOS transistors are used as pull-up network and NMOS transistors are used as pull-down network. And because of that, the static power consumption of the CMOS based logic gates and logic circuit is very low compared to the logic gates which is designed using only either NMOS or PMOS transistors. Moreover, CMOS based logic gates has higher noise margin compared to NMOS and PMOS based logic gates.

NMOS Inverter and the Issue of Power Dissipation with NMOS and PMOS Transistors

Using just either NMOS or PMOS transistors also, it is possible to design a logic gate. The basic design of NMOS inverter is shown below.

Let’s assume that the threshold voltage (V_T) of the NMOS transistor is 0.5 V. When V_GS = 5V or when V_GS > V_T , (Let’s assume that logic ‘1’ is 5V) then MOSFET will be ON and acts as a close switch (Ideally, the ON resistance of the MOSFET is 0 ohm) And the output will get connected to the ground. But actually, there will be some finite ON resistance of the MOSFET (10s of Ohm). And the drain resistor R_D is in kilo-ohm. Therefore, in actual case also, the output will be very close to 0V or logic ‘0’.

Similarly, when V_GS = 0V or logic ‘0’ then MOSFET will be OFF and it will act as a open switch. And through the drain resistor, the output will get connected to the supply voltage. That means when input is 0 then output is V_DD.

And in this way, this circuit will act as an inverter.

Now, when we are designing this logic gate using a discrete components, then it is possible to include large drain resistor in the circuit. But in the integrated circuits, it is difficult to fabricate a resistor with a large value.
Therefore, in the ICs, instead of resistor, the MOSFET is used as an active load.
As shown below, the gate and drain terminals of the MOSFET are connected to V_DD. That means the upper NMOS transistor remains in the ON condition. And in the ON condition, its ON resistance will provide the required drain resistance for the Lower NMOS transistor.

Of course, by changing the MOSFETs device parameters, it is possible to ensure that, its ON resistance is in kΩ.

The issue with this design is that, there is a static power dissipation across the transistor.
For example, when the input to the inverter is ‘1’ then NMOS will be ON, and it provides very low resistance. And because of that, there is power dissipation across the NMOS transistor.
That means, if the input to the inverter is a clock signal which is continuously changing between ‘1’ and ‘0’ then for half of the total time, there will be a static power dissipation across the NMOS transistors.
And the same is case with the logic gate designed using PMOS transistors.

That means when we are designing the logic gates only using NMOS or PMOS transistors then there will be a static power dissipation. And the power dissipation becomes a critical factor when there are millions of such transistors in the circuit.

NMOS passes weak logic ‘1’ and Strong logic ‘0’

Apart from the power dissipation, the other issue with the NMOS transistor is that, it passes weak logic ‘1’.

When the input to the inverter is logic ‘0’, then output of the inverter should be high and ideally, it should be equal to V_DD. But actually, here the output will not go beyond V_DD – V_T.

Because, if output of the inverter goes to 5V, then the source terminal of the upper NMOS transistor will be at 5V and therefore, V_GS will become 0V.
Now, for MOSFET to be in ON condition, V_GS should be more than V_T. That means in this case, the voltage at the source terminal of the upper MOSFET won’t go beyond V_DD – V_T.
Otherwise, the upper NMOS transistor will become OFF.
So, for example, if threshold voltage of NMOS is 0.5V and supply voltage is 5V then output will not go beyond 4.5 V.
That means we will not get full voltage swing. Or in other words, NMOS is weak to pass logic ‘1’.

But at the same time, NMOS transistor passes strong logic ‘0’.

For example, if the input to the inverter is logic ‘1’ then NMOS will be in the ON condition and since source is connected to the ground, it will pull down the voltage of the drain terminal to 0V.
That means NMOS passes weak logic ‘1’ but it passes logic ‘0’. And it can be used in the pull-down network to pull down the voltage of specific node to 0V.

PMOS passes strong logic ‘1’ and weak logic ‘0’

As shown below, here the source of PMOS is connected to 5V and drain is connected to capacitor.

Now, when input to PMOS is 0V then V_SG is more than V_T and PMOS will act as a closed switch.
So, capacitor at the drain terminal will start charging towards 5V and eventually the voltage at the drain terminal will be equal to 5V.
So, when we want to pull-up the voltage at the drain terminal to the supply voltage, then we can use the PMOS transistors.
But PMOS transistor is weak for passing logic ‘0’.

Let’s say now the drain terminal is connected to ground. And capacitor is connected at the source terminal. And let’s assume that, initially, the voltage across the capacitor is 3V.
So, now when V_G = 0V, then V_SG is more than V_T, and because of that, PMOS will conduct and it will try to bring down the voltage of the source terminal to 0V.
So, capacitor will start discharging. But as soon as the voltage at the source terminal reaches threshold voltage, then MOSFET will be turned off. Because now V_SG = V_T.
That means the voltage at the source terminal cannot go below threshold voltage.
So, for example, if the threshold voltage of the MOSFET is 0.5V then the voltage at the source terminal will not go below 0.5V. That means PMOS is weak to pass logic ‘0’.

And that is why it not preferable to use the PMOS transistor in the pull-down network. But it can be used in the pull-up network where we want to pull up the voltage of the specific node.

In the CMOS network both PMOS and NMOS transistors are used. The PMOS is used as a pull up network and NMOS transistors are used in the pull-down network.
And because of this configuration, there is almost no static power consumption in the CMOS logic gates.

CMOS Inverter

As shown below, PMOS transistor is used as a pull-up transistor, so its source is connected to supply voltage and drain is connected to the output node.

Similarly, the NMOS transistor is used as a pull-down transistor. That means its source terminal is connected to ground terminal and drain is connected to output node.
And the gate terminals of both PMOS and NMOS transistor is connected to the input.

Working of CMOS Inverter:

When input is low or logic ‘0’, then V_SG > V_T for this PMOS transistor and that’s why PMOS will be ON. On the other end, for NMOS transistor, V_GS < V_T.
that means when input is logic ‘0’, PMOS transistor will be ON and NMOS transistor will be OFF.
And that’s why the output will be connected to 5V.
Moreover, since PMOS passes strong logic ‘1’ , the output will be very close to supply voltage.
That means when V_in is logic ‘0’ then output is logic ‘1’.

On the other end, when Vin is logic ‘1’, then PMOS will be OFF and NMOS will ON.
So, in that case, the NMOS transistor will pull-down the output voltage to logic ‘0’. And since NMOS passes strong ‘0’, so output will be very close to 0V.

So, in this way, at any given time either PMOS transistor is ON or NMOS transistor is ON. And there is no direct path from supply to ground.
And because of that, the static power consumption of CMOS logic gate is almost negligible.

Implementation of Logic Gates using CMOS Logic

In general any CMOS based logic gate consist of Pull-up network and pull-down network. The pull-up network consists of PMOS transistors while pull-down network consist of NMOS transistors. And inputs to both networks are same.

So, we have already discussed about the CMOS inverter. Similarly, let’s see how to design other logic gates using CMOS logic.

Implementation of NAND and NOR gate using CMOS Logic:

NAND Gate:

For two input NAND gate, if A and B are the inputs then its output Y = (A.B)’.

In NMOS network when we have AND operation between the two variables, then two NMOS transistors will get connected in series. And the output will be complement of it.

The PMOS network is dual of the NMOS network. In the NMOS network, if two transistors are connected in series then in the PMOS network, the two PMOS transistors will get connected in parallel.

NOR Gate:

For two input NOR gate, if A and B are the inputs then its output Y = (A+B)’.

In the NMOS network, whenever there is an OR operation between the two variables then two NMOS transistors will get connected in parallel. And the output will be complement of it.

The PMOS network will be the dual of the NMOS network. Therefore, in the PMOS network, the two PMOS transistors will get connected in series.

Implementation of AND and OR gate using CMOS Logic:

OR Gate:

To implement the OR gate, just add the inverter at the output of the NOR gate. The CMOS OR gate is shown below.

AND Gate :

Similarly, by connecting the inverter at the output of the NAND gate, we can implement AND gate. The CMOS AND gate is shown below.

Implementation of XOR Gate and XNOR using CMOS Logic :

Similarly, the implementation of XOR and XNOR gate is shown below.

XOR Gate:

XNOR Gate :

For more information, check this video on CMOS Logic gates.

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Understanding Binary Multiplication:

The binary multiplication is similar to the conventional decimal multiplication. In Binary Multiplication, the each digital of the second number is multiplied with each digit of the first number. The first number in the multiplication is known as the “Multiplicand” and the second number is called as “Multiplier”.

In binary multiplication, each digit of the multiplier is multiplied with the multiplicand. Each multiplication gives the partial products. The partial products are adjusted according to their weights. And the summation of the partial products gives us the final result of the multiplication.

Since the binary numbers involves only two digits (1s and 0s), the binary multiplication process in much simpler than decimal multiplication.

In binary multiplication,

0 x 0 = 0

0 x 1 = 0

1 x 0 = 0

1 x 1 = 1

Using these simple rules of binary multiplication, it is possible to multiply two numbers.

Let’s take one example and through that let’s understand the process of binary multiplication.

Example 1

Let’s say, we want to multiply 6 (110) and 5 (101) in binary.

To perform the binary multiplication, starting from the LSB of the multiplier, we will multiply each digit to the multiplicand.

So, if we start from 1 then first, we will multiply it with 0, then 1 and at the last with this MSB (1).

Now, when we are multiplying the binary digits, then actually we are also multiplying their weights. And according to their weights, we will place the result in a particular column.

So, here first let’s multiply this 1 with 0. So, here the weight of both 0 and 1 is 2⁰. So, let’s multiply their weights separately.

So, as you know 1 x 0 is 0. And this 2⁰ x 2⁰ is also 2⁰. That means we will place the result in 2⁰ column.

Similarly, when we multiply 1 with 1 then actually it is (1 x 1) ( 2⁰ x 2¹ ) = 1 x 2¹ .

Therefore, the result will be placed in 2¹ column.

Likewise, when we multiply 1 (the LSB of multiplier) with 1 (MSB of multiplicand), then actually it is (1 x 1) (2⁰ x 2²) = 1 x 2² . Therefore, the result will be placed in 2² column.

The result of the multiplication is known as the partial product. The first partial product is shown below.

Similarly, the second digit of the multiplier will be multiplied with the each digit of the multiplicand. And the result will be placed in appropriate columns according to their weights. The same is shown below.

And finally, the MSB of the multiplier will be multiplied with the each digit of the multiplicand. And once again the result will be placed in an appropriate columns according to their weights. The same is shown blow.

In this way, in the multiplication process, we got three partial products. As you can observe, the value of partial product is either 0 or, its value is same as the multiplicand. If the digit of the multiplier is 0 then partial product is 0 and if the digit of the multiplier is 1 then partial product is same as the multiplicand.

Also, as you can observe, as we move from LSB to MSB of the multiplier, each partial product is left shifted by 1 bit position. So, once we get all our partial products then final step is to add all the partial products to get the final result of the multiplication.

Once we add all the partial products, then result is 11110. Its decimal equivalent is 30. And in this way, we can perform the binary multiplication of two unsigned binary numbers. Let’s take another example to understand the multiplication procedure.

Example 2

Let’s say, we want to multiply 12 (1100) and 13 (1101). So, here 12 is multiplicand and 13 is a multiplier. Starting of the LSB of the multiplier, let’s multiply each digit with the multiplicand.

Since the first digit is of the multiplier is 1, the partial product is same as the multiplicand. If we move to the next digit of the multiplier, then it is 0. Since it is 0, the partial product will be 0. But it will be left shifted by 1 bit position.

Similarly, the next two bits are 1. So, partial product will be same as the multiplicand. But each partial product will be left shifted by 1 bit position. The same is shown below.

The final step is to add all the partial products to get the result of the multiplication. If we add all the partial products then result is 10011100.

In this way, it is possible to multiply two unsigned binary numbers. Similarly, now let’s see the multiplication procedure for fractional binary numbers.

Multiplication of Fractional Binary Numbers

The multiplication of fractional binary number is similar to the binary integers. Let’s take one example and through that, let’s understand the multiplication procedure. Let’s say, we want to multiply 6.25 and 3.5.

In the binary, two numbers are 110.01 and 11.10. In the first number (110.01), the number of digits after the binary point are 2. Similarly, in the second number (11.10), the number of digits after the binary point are 1.

First of all, let’s write the two numbers without their binary points. And let’s multiply the two numbers like a binary integers. For the multiplication, align the two numbers from the LSB positions.

After multiplying the two numbers, the result will be 10101111.

Now, we just need to put the binary point at the appropriate location. In the first number 6.25 (110.01) the number of digits after the binary point are 2. And similarly, in the second number 3.5 (11.1), the number of digits after the binary point are 1. The total number of digits are 3 (2 +1). Therefore, in the obtained result, put the binary point after the 3 digits from the LSB.

And therefore, the result after the multiplication is 10101. 111. If we see its binary equivalent then it is equal to 21.875. In this way, we can multiply two fractional binary numbers.

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Power Supply rejection Ratio (PSRR) specifies that if there is any change in the supply voltage, then how it will affect the output of the op-amp. For op-amp, if there is any change in the supply voltage, then it should not affect the output of the op-amp. With the change in the supply voltage, the output voltage of the op-amp will also change by a small margin. And this is specifically important when the input signal level is very small. This PSRR is specified in terms of the input offset voltage. That means with the change in the supply voltage, how the input offset voltage of the op-amp will change. And typically, the unit of this PSRR is μV / V.

Where,

ΔVio= change in the input offset voltage

ΔVs= change in the supply voltage

For example, for some op-amp if the PSRR is equal to 10 μV / V, it means that when the supply voltage will change by 1 volt, then the input offset voltage of that op-amp will change by a 10 μV. The change in the input offset voltage will lead to the change in the output of the op-amp.

For dual supply op-amps typically it is assumed that the change in the supply voltage is symmetrical. But if the change in the supply voltage is not symmetrical, then it will lead to the common mode error.

In the decibel this PSRR is defined as

Effect of Supply Voltage on input offset voltage of the op-amp

Internally, the first stage of the op-amp consist of differential amplifier. For the differential amplifier, if both the transistors are identical then if we apply the same input at both terminals, then output of the op-amp should be zero. But because of some mismatch between the two transistors, there will be some finite differential output. And that differential output will get amplified by the gain of the op-amp. Hence there will be some finite output voltage even if both input terminals are connected to the same input terminal. The input offset voltage is the additional input voltage that we need to apply between the two input terminals, to make the output of the op-amp zero.

With the variation in the supply voltage, the biasing of the differential amplifier will change and hence, the input offset voltage of the op-amp will also change.

The change in the input offset voltage will lead to the change in the output of the op-amp. If the op-amp is configured in the closed loop configuration (inverting or non-inverting), then the input offset voltage will get multiplied by the noise gain of the op-amp.

The Power Supply Rejection Ratio (PSRR) is the ability of the op-amp to withstand the change in the supply voltage. The smaller value of PSRR (μV/ V) is preferable. If PSRR is specified in dB, then larger value of PSRR is preferable.

PSRR with Frequency

PSRR value will also reduce with the frequency. That means if we have a ripple let’s say of 100 Hertz on top of the supply voltage, then that ripple will not be rejected by the op-amp as effectively as the DC voltage. And because of that, some fraction of that ripple will also appear at the output of the op-amp.

The below figure shows the typical PSRR curve with frequency. As the frequency increases, the PSRR (in dB) reduces.

Therefore, to reduce the effect of high frequency ripple on the output of the op-amp, it is advisable to use a well regulated supply voltage with the op-amp. And to avoid any high frequency noise in the output, the proper value of the decoupling capacitor should always be used with the op-amp. The decoupling capacitors provides the low impedance part to the high frequency noise. And in a way it reduces the effect of the high frequency noise at the output of the op-amp.

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Race Around Condition in JK Flip-Flop

In the level triggered JK flip-flop when, when both J and K input are 1 and when the ON time of the clock is more than the propagation delay of the flip-flop then the output of the flip-flop will toggle continuously between ‘1’ and ‘0’. And because of that, it is difficult to predict the output of the flip-flop once the clock becomes low. The race around condition in undesirable condition in the flip-flop, and should be avoided to get the reliable flip-flop output.

Race Around Condition in JK Flip-Flop

Using the JK flip-flop in master slave configuration, this race around condition can be avoided.

Circuit Diagram of Master Slave JK Flip-Flop

Circuit Diagram of Master Slave JK Flip-Flop

As shown in the above figure, it consist of two gated SR latches. The first latch act as a master latch and the second latch act as a slave latch. The output of the master latch is connected to the slave latch. The Q’ output of the slave latch is connected back to the master latch where J input is applied and similarly, Q output is connected back where the K input is applied. The clock signal to the slave latch is applied through an inverter. That means when clock signal is high then master is enabled and slave is disabled. And similarly, when clock is low then slave is active and master is disabled.

Working of Master Slave JK Flip-Flop

Let’s understand the working of Master Slave JK flip-flop using timing diagram.

Timing Diagram of Master Slave JK Flip-Flop

Here, initially it has been assumed that the outputs of both master and slave are 0. (Both M and Q are 0). When the clock signal is high then master latch will get enabled and will respond to the input signals. In this case, initially during the first clock, J = 0 and K = 1. So, output of the master latch will be 0. During ON time of the clock, the slave latch will remain disabled and it will hold its current state. Similarly, during the OFF time of the clock, the master will get disabled and it will hold its current state. And at the same time, the slave latch will become active and will follow the master output. That means, the slave latch is following the master output during the off time of the clock. Or in other words, the slave latch follows the master output after the delay of T_ON . Where T_ON is the ON time of the clock signal. This cycle repeats at every clock cycle.

During the ON time of the second clock, since J = 1 and K = 0, so master output M = 1. And the slave output Q will remain 0. (Since it is disabled) The slave latch will follow the master output during the OFF time of the clock. From the timing diagram, you can see that, the slave is following the master output after the delay of T_ON.

For more information, please go through this video on the master slave flip-flop.

Master Slave SR Flip-Flop and D Flip-Flop

Similar to the master slave JK flip-flop, the master slave D flip-flop and SR flip-flop can be designed.

The circuit diagram of the master slave SR flip-flop is shown below.

Master Slave SR Flip-Flop

In a simplified manner, this is how it can be represented.

Similarly, using two gated D latches, the master slave D flip-flop can be designed.

Master Slave D Flip-Flop

The master slave flip-flop circuit works correctly when the input is constant during the ON time of the clock. If the input signal changes during the ON time of the clock, then slave will not be able to follow the master output. The same is shown in the below timing diagram.

As you can see in the timing diagram, during the second clock cycle, the D input is changing during the ON time of the clock. Since the master is ON at that time, so master will follow the change in the input signal. But the slave will not be follow that input change. Because the slave is following the master output during the OFF time of the clock. Just at the end of the ON period of the second clock, the master output M is 1, so slave will follow the same output. That means, the slave is not able to follow the master output completely when the input is changing during the ON time of the clock.

That means, to use the master slave flip-flop in a correct manner, we need to ensure that the input is not changing during the ON time of the clock.

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In the SR Flip-Flop, when both inputs S and R are 1 then the output of the flip-flop is indeterminate. That issue can be resolved using the JK Flip-Flop. Similar to the SR Flip-Flop, the JK flip-flop has two inputs. And using the two inputs the flip-flop can be set, reset, hold (memory) or toggled. Unlike the SR flip-flop, in the JK flip-flop, when both inputs J and K are 1 then the output of the flip-flop toggles. The symbol of edge triggered JK flip-flop and its truth table is shown below.

JK Flip-Flop Symbol and Truth Table

In the JK flip-flop, at the rising edge of the clock, when J = 0 and K = 0 then flip-flop retains (holds) the current state. When J = 0 and K = 1, then flop-flop resets to 0. When J = 1 and K = 0, then flip-flop sets the output to 1. And when J = 1 and K = 1 then output of the flip-flop toggles. When the clock signal is low, then irrespective of the value of J and K inputs, the flop-flop retains the present state. The detailed truth table with all different possibilities of Qn, J and K inputs are shown below, where Qn is the present state and Q_n+1 is the next state of the flip-flop.

JK Flip-Flop Truth Table

The negative edge triggered JK flip-flop is similar to the positive edge triggered flip-flop. But it responds to the inputs only at the falling edge of the clock. The symbol and truth table of negative edge triggered flip-flop is shown below.

Symbol and Truth Table of Negative Edge Triggered JK Flip-Flop

JK Flip-Flop Circuit Diagram

With the little modification in the circuit of the SR flip-flop circuit, it can be used as the JK flip-flop. The circuit of JK flip-flop is shown below.

Circuit Diagram of Positive Edge Triggered JK Flip-Flop

As you can see from the circuit diagram, in the RS flip-flop circuit, the K input is applied in place of the R input while the J input is applied in place of the S input. Moreover, there is a feedback from output to input side. The Q output is connected back the AND gate where the K input is applied while the Q’ output is connected back to the AND gate where the J input is applied. Here the clock transition circuit generates the narrow pulses at the every clock transition. The same is applied to the enable input of the latch. And in this way, the gated latch behaves as an edge triggered flip-flop.

The same circuit can also be implemented using the NAND gates. The circuit diagram of the JK flip-flop with the NAND gates is shown below.

Circuit Diagram of Positive Edge Triggered JK Flip-Flop (using NAND gates)

JK Flip-Flop Characteristic Equation

The characteristic equation shows the output of the flip-flop Q _n+1 in terms of the present state Q _n and the current inputs J and K. The characteristic table of the JK flip-flop is shown below.

The characteristic Table of JK Flip-Flop

As per the characteristic equation, the output Q _n+1 is ‘1’ for 4 different input combinations. ( 4 minterms). Using the K-map, the algebraic expression can be simplified further.

As per the K-map, after the simplification the output of the flip-flop or the characteristic equation

JK Flip-Flop Excitation Table

The excitation table of the flip-flop shows the required excitation to the flip-flop, or the required input to the flip-flop, to go from the given state to the next particular state. The excitation table of the JK flip-flop is shown below. In the table, ‘X’ represents that the value of input variable can be either ‘0’ or ‘1’.

Excitation Table of JK Flip-Flop

For more information, please check the video on JK Flip-Flop

JK Flip-Flop Timing Diagram

The below timing diagram shows, how the positive edge triggered JK Flip-Flop behaves when J and K input changes with time. Since it is a positive edge triggered flip-flop, so it will respond to the inputs only at the rising edge of the clock.

Timing Diagram of JK Flip-Flop

At the first rising edge of the clock, when J = 0 and K = 1, then output Q becomes 0 and it remains in that state until next rising edge. In between, even if the input changes, the flip-flop does not responds to the input changes.

At the second rising edge, since J = 1 and K = 0, the output of the flip-flop becomes 1. And it remains in that state until next rising edge.

At the third rising edge, since both J and K inputs are 1, the output of the flip-flop toggles and it becomes 0.

Race Around Condition in JK Flip-Flop

In the level triggered JK Flip-Flop, when J=K=1, and the ON time of the clock is more than the propagation delay of the JK Flip-Flop ,then because of the feedback from output to the input, the output of the flip-flop may toggle continuously between ‘1’ and ‘0’. This condition is known as the Race Around condition. Because of the Race Around Condition’, we cannot predict the output of the flip-flop at the end of the clock. It can be either ‘0’ or ‘1’. That’s why this Race Around Condition is undesired in the JK Flip-Flop. The issue of Race Around Condition can be resolved using the Master-Slave Flip-Flop. The below diagram shows the Race Around Condition in the JK Flip-Flop.

Race Around Condition in the JK Flip-Flop

The post JK Flip-Flop Explained | Race Around Condition in JK Flip-Flop | JK Flip-Flop Truth Table, Excitation table and Timing Diagram appeared first on ALL ABOUT ELECTRONICS.

The T flip-Flop has one input. When the input is 1 then its output toggles. Let’s say the present state of the flip-flop is Qn. So, with T = 1, if Qn = 0 then in the next state, the output of the flip-flop Qn+1 will become 0. And similarly currently if Qn is 1 then in the next state, the output will become 0.

With T = 1 input, since the output of the flip-flop toggles at every clock pulse, so it is known as T flip-flop. When T = 0, then the flip-flop will remain in the same state. The symbol and the truth table of the T flip-flop is shown below.

The symbol which is shown above is the symbol of the positive edge triggered flip-flop. The triangle in the symbol indicates that, the flip-flop responds to the input only at the rising edge of the clock. Similarly, the symbol of the negative edge triggered ?T flip-flop is shown below.

Characteristic Equation of T Flip-Flop

The characteristic equation of the flip-flop is the algebraic representation of the next state of the Flip-Flop (Q_n+1) in terms of the present state (Q_n) and the current input (T).

That means, here the input variables are Q_n and T, while the output is Q_{n+1 .}

From the truth table, as you can see, the output Q _n+1 is 1 for two different input combination of Q_n and T.

Let’s write down these two input combinations in the K-map, and let’s try to simplify the Boolean expression.

From the K-map, the two minterms are T Q_n ‘ and T ‘ Q_n . That means the characteristic equation of the T flip-flop is

Excitation Table of T Flip-Flop

The excitation table of the flip-flop shows the required excitation to the flip-flop, or the required input to the flip-flop, to go from the given state to the next particular state. For the T input, when T = 0 then the flip-flop remains in the same state and when T = 1 then the output of the flip-flop toggles at every clock pulse. The excitation table of the T flip-flop is shown below.

Circuit Diagram of T Flip-Flop

With the little modification, the JK flip-flop can be used as a T flip-flop. The truth table of the T flip-flop is shown below.

As you can see form the truth table, when both inputs of JK flip-flop are 0 then it hold the current state. And when its both inputs are 1, then the output of the flip-flop toggles. That means by connecting both inputs of the JK flip-flop together, it can be used as a T flip-flop.

That means with the little modification in the circuit of the JK flip-flop, it can be used as a T flip-flop. The circuit of the T flip-flop is shown below.

For more information, check this video on T flip-Flop.

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Half Adder

The half adder is the logic circuit that adds the two bits and generates the sum bit (S) and carry bit (C) as an output. The truth table of the half adder is shown below.

As per the truth table, the sum output is 1 for two input combinations. That means when A is 1 and B is 0 OR A is 0 and B is 1.

Algebraically, S = A’ B + A B’ = A ⊕ B

Likewise, the carry output is logic ‘1’ only for one input combination (when A = 1 and B = 1).

If we denote the carry output as C, then C = AB

Figure. 1 shows the Boolean expression and the logic circuit of the half adder.

Fig. 1 The Boolean expressions and the logic circuit of the Half Adder

The half adder circuit is suitable for the addition of two bits at the LSB (Least Significant Bit) position. Because during the addition of two bits at the LSB position, there is no incoming carry. But whenever there is an incoming carry (C_in) along with the two bits, then a full adder circuit can be used.

Full Adder

The full adder is the combinational circuit that adds the two bits along with the incoming carry (C_in) and generates the sum bit (S) and an outgoing carry bit (C_out) as an output. The truth table of the full adder is shown below.

As per the truth table of the full-adder, the sum and carry outputs are logic ‘1’ for 4 different input combinations. So, let’s find the simplified algebraic expression of sum (S) and carry (C_out)

Similarly, using the K-map, it is possible to find the simplified boolean expression for the carry output. The K-map for the carry output of the full adder is shown below.

After the simplification, the carry output C_out = AB + B C_in + AC_in

Moreover, the carry output can also be written as follows:

Based on these Boolean expressions, the logic circuit for the sum (S) and the carry (C_out) output is shown below.

As it can be seen from the logic circuit, we require 5 two-input gates and 1 three-input gate to implement the full adder. So, in total, we require 6 logic gates. But using another expression of C_out (C_out = AB + Cin ( A ⊕ B) ), we can reduce the total number of gates.

The same circuit is shown below. And if you closely observe then the circuit consist of two half-adders and one OR gate.

The same thing can also be shown in terms of the Half adder blocks.

For more information, do check this video on Half Adder and Full Adder.

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The logic gates are very basic building blocks of digital systems.

The logic gates are electronic circuits that consist of one or more inputs and one output. The relation between the input and output is based on certain logic. The logic gates have the ability to make certain logical decisions. And because of its ability to make these logical decisions, these gates are known as logic gates. By interconnecting or cascading the different logic gates, it is possible to implement various Boolean functions.

Types of Logic Gates

Here is the list of the different logic gates.

1. AND
2. OR
3. NOT
4. NAND
5. NOR
6. X-OR (Exclusive OR)
7. X-NOR (Exclusive NOR)

The AND, OR, and NOT are three basic logic gates. Using these three gates, it is possible to design and logic circuits or it is possible to implement any Boolean function.

The NAND and NOR are Universal Logic Gates. Because using any of the two gates alone, it is possible to implement any Boolean function or logic circuit. Apart from that, the other two gates are X-OR and X-NOR gates.

AND Gate

The logic symbol and the Boolean expression of the AND gate are shown below.

The output of the AND gate is 1 when all the inputs are high or logic ‘1’. If any one of the inputs is low or logic ‘0’ then the output of the AND gate is low. The truth table of the AND gate is shown below.

Similar to the 2-input AND gate, more than 2 input AND gates are also available. The symbol of the 3-input AND gate and its Boolean expression is shown below.

OR Gate

The logic Symbol and the Boolean expression of the OR gate are shown below.

The output of the OR gate is low or logic ‘0’ when all the inputs are low. If any one of the inputs is high then the output of the OR gate is high or logic ‘1’. The truth table of the 2-input OR gate is shown below.

Similarly, we can also have an OR gate with more than 2 inputs. The logic symbol of the 3-input OR gate and the corresponding Boolean expression is shown below.

NOT Gate

The NOT gate is also known as the inverter gate. Because the output is the complement of the input signal. The logic symbol and the Boolean Expression of the NOT gate are shown below.

The NOT gate inverts the Logic ‘0’ to Logic ‘1’ and Logic ‘1’ to Logic ‘0’. The truth table of the NOT gate is shown below.

NAND Gate

The symbol of the 2-input NAND gate is shown below. It is similar to the AND gate, but there is a bubble on the output side. The NAND gate is the combination of the AND gate followed by the NOT gate. That means the output of the NAND gate is equivalent to the output of the AND gate followed by the NOT gate.

Logic Symbol and the equivalent logic circuit of the NAND gate

Here is the truth table of AND gate followed by NOT gate. The inputs are A and B. Z is the output of the AND gate, while Y is the output of the NOT gate. Z’ (Z- bar) is the same as the output of the 2-input NAND gate. The output of the NAND gate is logic ‘0’ when all the inputs are high. When any one of the inputs is logic ‘0’ or all the inputs are logic ‘0’ then output is logic ‘1’.

NOR Gate

The symbol of the 2-input NOR gate is shown below. It is similar to the OR gate, but there is a bubble on the output side. The NOR gate is the combination of the OR gate followed by the NOT gate. That means the output of the NOR gate is equivalent to the output of the OR gate followed by the NOT gate.

Here is the truth table of OR gate followed by NOT gate. A and B are the inputs. Z is the output of the OR gate. Y is the output of the NOT gate. Z’ (Z- bar) is the same as the output of the 2-input NOR gate. The output of the NOR gate is logic ‘1’ when all the inputs are low. When any one of the inputs is logic ‘1’ or all the inputs are logic ‘1’ then output is logic ‘0’.

For more information about the different logic gates, check this video.

XOR gate

The logical symbol and the truth table of the 2 input XOR gate are shown below.

The Logic Symbol and Truth Table of 2 input XOR gate

As It can be seen from the truth table, the output of the 2-input XOR gate is logic ‘1’ when both inputs are different.

XNOR gate :

The Symbol of the 2-input XNOR gate is shown below. It is similar to the XOR gate, but there is a bubble at the output side. The XNOR gate is the combination of the XOR gate, followed by the NOT gate.

The logic Symbol and the Equivalent logic circuit of the XNOR gate

The truth table of the two-input XNOR gate is shown below. As you can see, the output of the two input XNOR gate is logic ‘1’ when both inputs are the same. when both inputs are different, the output is logic ‘0’.

The Truth Table of the 2-input XNOR gate

These logic gates (XOR and XNOR) gates are very useful in designing the arithmetic and code converter circuits.

Typically, more than 2-input XOR and XNOR gates are not readily available and they are designed using the 2-input gates.

For more information about XOR and XNOR gate, check this video.

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Multiplexing is a technique that allows the simultaneous transmission of multiple signals through a single channel or link. In multiplexing, several signals are combined into a single composite signal and transmitted over a single channel or medium. Using multiplexing the channel bandwidth can be utilized more efficiently or more signals can be transmitted through a channel at the same time.

Types of Multiplexing :

Although there are several types of multiplexing techniques, but mainly there are three multiplexing techniques.

1. Frequency Division Multiplexing (FDM)
2. Time Division Multiplexing (TDM)
3. Wavelength Division Multiplexing (WDM)

What is Frequency Division Multiplexing?

In Frequency Division Multiplexing, the different message signals are modulated at the different carrier frequencies. In this way, the modulated signals are separate from each other in the frequency domain. The modulated signals are combined together to form the composite signal and this signal is sent over the shared medium or channel. To avoid the interference between the two message signal, some guard band is also kept between the two message signals.

Fig. 1 shows the general block diagram of the Frequency Division Multiplexing scheme.

Fig.1 General Block diagram of Frequency Division Multiplexing

As shown in Fig.1, three different message signals are modulated at different carrier frequencies. And then they are combined into a single composite signal. The carrier frequencies of each signal should be selected such that there is no overlapping of two modulated signals. In this way, in the multiplexed signal, each modulated signal is separated from each others in the frequency domain. (as shown in Fig.2)

Fig.2 Frequency Division Multiplexing Technique

At the receiver, using the bandpass filter, each modulated signal is separated from the composite signal and demultiplexed. And by passing the demultiplexed signal through the low pass filter, it is possible to recover each message signal. So, this is the typical Frequency Division Multiplexing scheme.

Applications of Frequency Division Multiplexing Technique

1. AM and FM radio Broadcast
2. Cable TV
3. Satellite Communication
4. Telemetry
5. Telephony Systems
6. Early Generation
7. Cellular Networks

Frequency Division Multiplexing Hierarchy in Analog Telephony System

Voice signals typically contains the information from 300 to 3500 Hz. And including some guard band, each voice signal is assigned a bandwidth of 4 kHz in the telephony system. Each voice channel is single sideband modulated and then multiplexed. In the first level of multiplexing, 12 voice signals are multiplexed. The multiplexed signal occupies the band from 60 kHz to 108 kHz or the total bandwidth of 48 kHz. The carrier frequency of each voice signal is 4 kHz apart from each other. And the multiplexed signal is called group.

In the next level, 5 such groups are multiplexed and form the supergroup. The supergroup has bandwidth of 240 kHz contains total 60 voice channels.

In the next level, 10 such super groups are multiplexed and forms the Master group. The master group contains total 600 voice channels or voice signals and occupies the total the bandwidth of 2.52 MHz.

Similarly, in the next level, 6 such master groups are combined to form a Jumbo group which contains total 3600 voice channels.

The multiplexing hierarchy in analog telephony system is shown in Fig. 3

Fig. 3 Multiplexing Hierarchy in Analog Telephony System

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